Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Memory-efficient algorithms for the verification of temporal properties
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Analysis of Timed Systems Using Time-Abstracting Bisimulations
Formal Methods in System Design
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Extending Promela and Spin for Real Time
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
On-the-fly symbolic model checking for real-time systems
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Forward Analysis of Updatable Timed Automata
Formal Methods in System Design
Checking Timed Büchi Automata Emptiness Efficiently
Formal Methods in System Design
Proving the Correctness of Multiprocess Programs
IEEE Transactions on Software Engineering
Checking Timed Büchi Automata Emptiness Using LU-Abstractions
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Efficient on-the-fly emptiness check for timed Büchi automata
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Coarse abstractions make zeno behaviours difficult to detect
CONCUR'11 Proceedings of the 22nd international conference on Concurrency theory
Efficient emptiness check for timed büchi automata
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Efficient emptiness check for timed Büchi automata
Formal Methods in System Design
Modeling and verifying hierarchical real-time systems using stateful timed CSP
ACM Transactions on Software Engineering and Methodology (TOSEM)
ACM Computing Surveys (CSUR)
Multi-core emptiness checking of timed Büchi automata using inclusion abstraction
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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Timed automata [Alur and Dill 1994] comprise a popular model for describing real-time and embedded systems and reasoning formally about them. Efficient model-checking algorithms have been developed and implemented in tools such as Kronos [Daws et al. 1996] or Uppaal [Larsen et al. 1997] for checking safety properties on this model, which amounts to reachability. These algorithms use the so-called zone-closed simulation graph, a finite graph that admits efficient representation and has been recently shown to preserve reachability [Bouyer 2004]. Building upon Bouyer [2004] and our previous work [Bouajjani et al. 1997; Tripakis et al. 2005], we show that this graph can also be used for checking liveness properties, in particular, emptiness of timed Büchi automata.