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Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
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Information and Computation
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Formal Methods in System Design
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CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
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RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
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Checking timed Büchi automata emptiness on simulation graphs
ACM Transactions on Computational Logic (TOCL)
Strict Divergence for Probabilistic Timed Automata
CONCUR 2009 Proceedings of the 20th International Conference on Concurrency Theory
Stochastic Games for Verification of Probabilistic Timed Automata
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Checking Timed Büchi Automata Emptiness Using LU-Abstractions
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Model checking probabilistic timed automata with one or two clocks
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
VeSTA: a tool to verify the correct integration of a component in a composite timed system
ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
Efficient detection of Zeno runs in timed automata
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Deep random search for efficient model checking of timed automata
Proceedings of the 13th Monterey conference on Composition of embedded systems: scientific and industrial issues
Efficient on-the-fly emptiness check for timed Büchi automata
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Coarse abstractions make zeno behaviours difficult to detect
CONCUR'11 Proceedings of the 22nd international conference on Concurrency theory
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Incremental verification of component-based timed systems
International Journal of Computer Applications in Technology
Efficient emptiness check for timed büchi automata
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Efficient emptiness check for timed Büchi automata
Formal Methods in System Design
Model checking of time Petri nets
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Fundamenta Informaticae - This is a SPECIAL ISSUE ON ASM'05
Beyond lassos: complete SMT-Based bounded model checking for timed automata
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FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Modeling and verifying hierarchical real-time systems using stateful timed CSP
ACM Transactions on Software Engineering and Methodology (TOSEM)
Multi-core emptiness checking of timed Büchi automata using inclusion abstraction
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Model checking for probabilistic timed automata
Formal Methods in System Design
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This paper presents an on-the-fly and symbolic technique for efficiently checking timed automata emptiness. It is symbolic because it uses the simulation graph (instead of the region graph). It is on-the-fly because the simulation graph is generated during the test for emptiness. We have implemented a verification tool called Profounder based on this technique. To our knowledge, Profounder is the only available tool for checking emptiness of timed Büchi automata. To illustrate the practical interest of our approach, we show the performances of the tool on a non-trivial case study.