Algebraic laws for nondeterminism and concurrency
Journal of the ACM (JACM)
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Characterizing finite Kripke structures in propositional temporal logic
Theoretical Computer Science - International Joint Conference on Theory and Practice of Software Development, P
Concurrent systems and inevitability
Theoretical Computer Science
Event fairness and non-interleaving concurrency
Formal Aspects of Computing
Design and validation of computer protocols
Design and validation of computer protocols
A partial approach to model checking
Papers presented at the IEEE symposium on Logic in computer science
Stubborn set methods for process algebras
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
Partial order reduction: linear and branching temporal logics and process algebras
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
A partial order approach to branching time logic model checking
Information and Computation
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Causal Ambiguity and Partial Orders in Event Structures
CONCUR '97 Proceedings of the 8th International Conference on Concurrency Theory
Model Checking and Modular Verification
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
Partial-Order Methods for Temporal Verification
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Partial-Order Reduction in the Weak Modal Mu-Calculus
CONCUR '97 Proceedings of the 8th International Conference on Concurrency Theory
Relaxed Visibility Enhances Partial Order Reduction
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Stubborn sets for reduced state space generation
Proceedings of the 10th International Conference on Applications and Theory of Petri Nets: Advances in Petri Nets 1990
All from One, One for All: on Model Checking Using Representatives
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
An Automata-Theoretic Approach to Branching-Time Model Checking (Extended Abstract)
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Partial-Order Methods for Model Checking: From Linear Time to Branching Time
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
ACTLS properties and Bounded Model Checking
Fundamenta Informaticae
Bounded Model Checking for the Universal Fragment of CTL
Fundamenta Informaticae - Concurrency Specification and Programming Workshop (CS&P'2001)
Minimizing the Number of Successor States in the Stubborn Set Method
Fundamenta Informaticae - Concurrency Specification and Programming Workshop (CS&P'2001)
Error-preserving local transformations on communication protocols
Software Testing, Verification & Reliability
Automatic verification of parameterised multi-agent systems
Proceedings of the 2013 international conference on Autonomous agents and multi-agent systems
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The ”state explosion problem” can be alleviated by using partial order reduction techniques. These methods rely on expanding only a fragment of the full state space of a program, which is sufficient for verifying the formulas of temporal logics LTL−X or CTL−X*(i.e., LTL or CTL* without the next state operator). This is guaranteed by preserving either a stuttering maximal trace equivalence or a stuttering bisimulation between the full and the reduced state space. Since a stuttering bisimulation is much more restrictive than a stuttering maximal trace equivalence, resulting in less powerful reductions for CTL−X*, we study here partial order reductions that preserve equivalences ”in-between”, in particular a stuttering simulation which is induced by the universal fragment of CTL:−X*, called ACTL−X* The reductions generated by our method preserve also branching simulation and weak simulation, but surprisingly, they do not appear to be included into the reductions obtained by Peled's method for verifying LTL−X properties. Therefore, in addition to ACTL−X* reduction method we suggest also an improvement of the LTL−X reduction method. Moreover, we prove that reduction for concurrency fair version of ACTL−X* is more efficient than for ACTL−X*.