Dynamically resizable binary decision diagrams

Authors:
Stergios Stergiou;Jawahar Jain
Affiliations:
Fujitsu Laboratories of America, Sunnyvale, CA, USA;Fujitsu Laboratories of America, Sunnyvale, CA, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

Citing 12
Cited 1

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication

IEEE Transactions on Computers
Efficient implementation of a BDD package

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Efficient breadth-first manipulation of binary decision diagrams

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Improving the Variable Ordering of OBDDs Is NP-Complete

IEEE Transactions on Computers
High performance BDD package by exploiting memory hierarchy

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Breadth-first manipulation of very large binary-decision diagrams

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The design of a cache-friendly BDD library

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Symbolic manipulation of Boolean functions using a graphical representation

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Streaming BDD manipulation for large-scale combinatorial problems

Proceedings of the conference on Design, automation and test in Europe
Binary Decision Diagrams

IEEE Transactions on Computers

Optimizing BDDs for time-series dataset manipulation

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present the architecture of a new Ordered Binary Decision Diagram library that is designed from the ground up to be space efficient. The main novelty lies in the library's node structure, which is modified at run-time to closely follow the variations in size of the stored OBDDs. We compare the new library with existing OBDD libraries on ACM/SIGDA and industrial circuits and report significant performance and space gains.