Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
DAC '94 Proceedings of the 31st annual Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Combining Top-down and Bottom-up approaches for ROBDD
Combining Top-down and Bottom-up approaches for ROBDD
Compositional Techniques for Mixed Bottom-Up/Top-Down
Compositional Techniques for Mixed Bottom-Up/Top-Down
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Analysis of composition complexity and how to obtain smaller canonical graphs
Proceedings of the 37th Annual Design Automation Conference
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
HS-ROBDD: an efficient variable order binary decision diagram
Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers
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Reduced Ordered Binary Decision Diagrams (ROBDDs) have traditionally been built in a bottom-up fashion. In this scheme, the intermediate peak memory utilization is often larger than the final ROBDD size, limiting the complexity of the circuits which can be processed using ROBDDS. Recently we showed that for a large number of applications, the peak memory requirement can be substantially reduced by a suitable combination of bottom up (decomposition based) and top down (composition based) approaches of building ROBDDs. In this paper, we focus on the composition process. We detail four heuristic algorithms for finding good composition orders, and compare their utility on a set of standard benchmark circuits. Our schemes offer a matrix of time-memory tradeoff points.