Communicating sequential processes
Communicating sequential processes
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ACM Transactions on Programming Languages and Systems (TOPLAS)
Three partition refinement algorithms
SIAM Journal on Computing
Distributed cooperation with action systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Multiparty Interactions for Interprocess Communication and Synchronization
IEEE Transactions on Software Engineering
Proceedings of the Fourth Annual Symposium on Logic in computer science
CCS expressions finite state processes, and three problems of equivalence
Information and Computation
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Using partial orders for the efficient verification of deadlock freedom and safety properties
Formal Methods in System Design - Special issue on computer-aided verification: special methods II
Coordinating first-order multiparty interactions
ACM Transactions on Programming Languages and Systems (TOPLAS)
Strategic directions in concurrency research
ACM Computing Surveys (CSUR) - Special ACM 50th-anniversary issue: strategic directions in computing research
Synthesis of concurrent systems with many similar processes
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Proof System for Communicating Sequential Processes
ACM Transactions on Programming Languages and Systems (TOPLAS)
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Communication and Concurrency
Architecting families of software systems with process algebras
ACM Transactions on Software Engineering and Methodology (TOSEM)
Proving Deadlock Freedom in Component-Based Programming
FASE '01 Proceedings of the 4th International Conference on Fundamental Approaches to Software Engineering
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
All from One, One for All: on Model Checking Using Representatives
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Exploiting Symmetry In Temporal Logic Model Checking
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Applying Enterprise JavaBeans: Component-Based Development for the J2EE Platform
Applying Enterprise JavaBeans: Component-Based Development for the J2EE Platform
Software Ecosystem: Understanding an Indispensable Technology and Industry
Software Ecosystem: Understanding an Indispensable Technology and Industry
The Art of Software Testing
Composition for component-based modeling
Science of Computer Programming - Formal methods for components and objects pragmatic aspects and applications
Modeling Heterogeneous Real-time Components in BIP
SEFM '06 Proceedings of the Fourth IEEE International Conference on Software Engineering and Formal Methods
Modeling Environment for Component Model Checking from Hierarchical Architecture
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Software Engineering
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
An Approach to Modelling and Verification of Component Based Systems
SOFSEM '07 Proceedings of the 33rd conference on Current Trends in Theory and Practice of Computer Science
A Polynomial-Time Checkable Sufficient Condition for Deadlock-Freedom of Component-Based Systems
SOFSEM '07 Proceedings of the 33rd conference on Current Trends in Theory and Practice of Computer Science
Everything Is PSPACE-Complete in Interaction Systems
Proceedings of the 5th international colloquium on Theoretical Aspects of Computing
Compositional analysis of deadlock-freedom for tree-like component architectures
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Using Architectural Constraints for Deadlock-Freedom of Component Systems with Multiway Cooperation
TASE '09 Proceedings of the 2009 Third IEEE International Symposium on Theoretical Aspects of Software Engineering
Model Checking as A Reachability Problem
RP '09 Proceedings of the 3rd International Workshop on Reachability Problems
Automatic Verification of Directory-Based Consistency Protocols
RP '09 Proceedings of the 3rd International Workshop on Reachability Problems
RP '09 Proceedings of the 3rd International Workshop on Reachability Problems
Deriving complexity results for interaction systems from 1-safe Petri nets
SOFSEM'08 Proceedings of the 34th conference on Current trends in theory and practice of computer science
Ensuring properties of interaction systems
Program analysis and compilation, theory and practice
Efficiently verifiable conditions for deadlock-freedom of large concurrent programs
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Analyzing component-based systems on the basis of architectural constraints
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
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We present a compositional analysis of deadlock-freedom in component systems with multiway cooperation. We require the systems to satisfy an architectural constraint which makes sure that the communication structure between the components is given by a tree. Only pairs of components have to be examined for the analysis, therefore the cost is polynomial in the size of the input.We shortly discuss a prototype algorithm which is based on our results and can be used for the investigation of deadlock-freedom of systems satisfying the architectural constraint.