Integrated Circuit Defect-Sensitivity: Theory and Computational Models
Integrated Circuit Defect-Sensitivity: Theory and Computational Models
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new quality estimation methodology for mixed-signal and analogue ICs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
13.1 A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
Journal of Electronic Testing: Theory and Applications
Insights on fault interference for programs with multiple bugs
ISSRE'09 Proceedings of the 20th IEEE international conference on software reliability engineering
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An extension of the well known defect level model by Williams and Brown has been proposed, to account for non-uniform distribution of fault occurrence probabilities. The field experiment reported by Maxwell and Aitken is interpreted in terms alternative (which may also be considered complementary) to those provided by the model by Agrawal, Seth and Agrawal. Some simulation experiments show that, for circuits implemented in standard cell style, there is a correlation between occurrence probabilities and testability values of SSA and BRI faults.