DESB, a functional abstractor for CMOS VLSI circuits
EURO-DAC '92 Proceedings of the conference on European design automation
SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
LOGEX—an automatic logic extractor form transistor to gate level for CMOS technology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A technology independent block extraction algorithm
DAC '84 Proceedings of the 21st Design Automation Conference
ACM Transactions on Embedded Computing Systems (TECS)
High-level modelling and exploration of coarse-grained re-configurable architectures
Proceedings of the conference on Design, automation and test in Europe
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper discusses the use of transistor abstraction to enable the functional verification of FPGA fabrics with RTL models. It first describes the multiplexer structures that are used on a massive scale in FPGAs and the specific challenges that they pose to transistor abstraction tools. It then reviews previous approaches and shows that the cone model of the DESB system is particularly well suited to abstract FPGA logic because it makes pass-gate branches in multiplexer structures well apparent. Based on this model, methods are described to isolate multiplexer structures, take into account logic correlation between signals, and generate RTL models that are both simulation efficient and highly readable. Finally, Altera's ABX tool that implements these concepts is briefly described.