A layout verification system for analog bipolar integrated circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Circuit recognition and verification based on layout information
DAC '81 Proceedings of the 18th Design Automation Conference
SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
SUBGEN: a genetic approach for subcircuit extraction
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Transistor abstraction for the functional verification of FPGAs
Proceedings of the 43rd annual Design Automation Conference
External memory layout vs. schematic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Functional block extraction is a useful tool for layout verification of integrated circuits. In particular, it facilitates the network comparison problem by transferring it to a higher level of hierarchy. This paper describes a computer program called BLEX (Block Extractor), which is able to extract any given circuit block, e.g., gates, flip-flops, memory cells, differential amplifiers, Darlington circuits etc., from a SPICE-like network description. The algorithm is fully technology independent. The size of the blocks is not subject to any restrictions. Descriptions of the functional blocks having the same format as the network description are supplied by the user. The circuit to be examined results usually from a preceding circuit extraction. The extractor and BLEX are part of the layout verification system ALAS (ALayout Analysis System).