The input/output complexity of sorting and related problems
Communications of the ACM
SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
LOGEX—an automatic logic extractor form transistor to gate level for CMOS technology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
External-memory graph algorithms
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
I/O-complexity of graph algorithms
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Efficient netlist comparison using hierarchy and randomization
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An Algorithm for Subgraph Isomorphism
Journal of the ACM (JACM)
External memory algorithms and data structures: dealing with massive data
ACM Computing Surveys (CSUR)
Efficient Subgraph Isomorphism Detection: A Decomposition Approach
IEEE Transactions on Knowledge and Data Engineering
A technology independent block extraction algorithm
DAC '84 Proceedings of the 21st Design Automation Conference
An Efficient External-Memory Implementation of Region Query with Application to Area Routing
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Netlist Processing for Custom VLSI via Pattern Matching
Netlist Processing for Custom VLSI via Pattern Matching
An improved layout verification algorithm (LAVA)
EURO-DAC '90 Proceedings of the conference on European design automation
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A computational study of external-memory BFS algorithms
SODA '06 Proceedings of the seventeenth annual ACM-SIAM symposium on Discrete algorithm
An External Memory Circuit Validation Algorithm for Large VLSI Layouts
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SubIslands: the probabilistic match assignment algorithm for subcircuit recognition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Solving difficult instances of Boolean satisfiability in the presence of symmetry
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The circuit represented by a VLSI layout must be verified by checking it against the schematic circuit as an important part of the functional verification step. This involves two central problems of matching the circuit graphs with each other (graph isomorphism) and extracting a higher level of circuit from a given level by finding subcircuits in the circuit graph (subgraph isomorphism). Modern day VLSI layouts contain millions of devices. Hence the memory requirements of the data structures required by tools for verifying them become huge and can easily exceed the amount of internal memory available on a computer. In such a scenario, a program not aware of the memory hierarchy performs badly because of its unorganized input/output operations (I/Os) as the speed of a disk access is about a million times slower than accessing a main memory location. In this article, we present I/O-efficient algorithms for the graph isomorphism and subgraph isomorphism problems in the context of verification of VLSI layouts. Experimental results show the need and utility of I/O-efficient algorithms for handling problems with large memory requirements.