Efficient netlist comparison using hierarchy and randomization

Authors:
J. D. Tygar;Ron Ellickson
Affiliations:
Aiken Computation Lab., Harvard U., Cambridge, MA;Valid Logic Systems, 2820 Orchard Pkwy., San Jose, CA
Venue:
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Year:
1985

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Abstract

Programs to compare the layout of ICs with their schematics have recently appeared. These programs have limited functionality and require large amounts of CPU time. We discuss the implementation of a fast [&Ogr;(n(log n)2)] logic comparison algorithm which uses hierarchy and randomization. This algorithm handles swappable components without performance degradation and is extremely robust in the presence of input errors. We include experimental data.