An improved layout verification algorithm (LAVA)

Authors:
Magdy S. Abadir;Jack Ferguson
Affiliations:
MCC CAD Program, Austin, Texas;MCC CAD Program, Austin, Texas
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

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Abstract

The correctness of a VLSI circuit layout can be verified by comparing the netlist extracted from the layout with the specification netlist. Ebeling and Zajicek [3, 4] showed that this problem can be solved by utilizing known techniques for solving classical graph isomorphism problem. In this paper we present an improved algorithm for solving the graph isomorphism problem associated with layout verification. This algorithm takes advantage of the hipartite nature of the graphs associated with the layout verification problem. The sum of the improvements in this algorithm tend to relieve the memory-intensive problems reported in [5], and accelerate the process.