PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
IEEE Transactions on Computers
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
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A method for PLA test, pattern generation based on a branch and bound algorithm that exploits function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branchin heuristic is presented. The algorithm handles extended fault models including crosspoint and delay faults. Heuristics which speed up test set genration and improve test set compaction are discussed. Results of tests on a wide range of benchmark PLAs are included.