Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
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Newly manufactured Field Programmable Logic Arrays (FPLA) often contain crosspoint defects. We present two techniques to mask out the crosspoint faults in standard off-the-shelf FPLAs. Our techniques do not rely on additional logic, hence the effective yield is enhanced with no additional hardware cost. The first method is a dynamic scheme which reconfigures the functional mask to render a faulty FPLA usable. The second method utilizes the unused product lines of the FPLA. With a sufficient number of excess product lines, we show that a defective FPLA is guaranteed to be rendered usable. We have obtained the probability measures for the usability of defective FPLAs both with and without the implementation of this technique.