Optimization theory with applications
Optimization theory with applications
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Arithmetic Spectrum Applied to Fault Detection for Combinational Networks
IEEE Transactions on Computers
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming
IEEE Transactions on Computers
Introduction to Logic and Switching Theory
Introduction to Logic and Switching Theory
Generalized Hopfield Neural Network for Concurrent Testing
IEEE Transactions on Computers
| Hi-index | 14.98 |
This paper considers the problem of applying neural network for logic circuit testing and proposes an efficient method based on hyperneural network (HNN). The HNN uses an energy function that not only considers binary relations but also captures all higher order relations among N neurons. We illustrate the hyperneural concept using two formulations. First, a constraint energy function is defined and the gate model is obtained. Second, the Hopfield network is reformulated to generate the gate level hyperneural model. The gate level HNN are used to give a mathematical form to the digital circuit that, in turn, requires optimization techniques to solve the test generation problem. We have used ISCAS'85 benchmark circuits to illustrate the method. Results are compared with those obtained from PODEM, MODEM, and FAN