CMOS stuck-open fault detection using single test patterns

Authors:
R. Rajsuman;A. P. Jayasumana;Y. K. Malaiya
Affiliations:
Department of Computer Engineering, Case Western Reserve University, Cleveland, OH;Department of Electrical Engineering, Colorado State University, Fort Collins, CO;Department of Computer Science, Colorado State University, Fort Collins, CO
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

Citing 5
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Abstract

CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. Two or multi-pattern sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods for augmenting CMOS gates to test CMOS stuck-open faults, are found to be inadequate in the presence of glitches. A new CMOS testable design is presented. The scheme uses two additional MOSFETs, which convert a CMOS gate to either pseudo nMos or pseudo pMOS gate during testing. The proposed design ensures the detection of stuck-open faults using a single vector during testing