Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor

Authors:
Y. Crouzet;C. Landrault
Affiliations:
Laboratoire d'Automatique et d'Analyse des Systemes du CNRS;-
Venue:
IEEE Transactions on Computers
Year:
1980

Citing 9
Cited 3

Principles of self-checking processor design and an example

Principles of self-checking processor design and an example
Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions

IEEE Transactions on Computers
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes

IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code

IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

IEEE Transactions on Computers
Partially Self-Checking Circuits and Their Use in Performing Logical Operations

IEEE Transactions on Computers
Note on Self-Checking Checkers

IEEE Transactions on Computers
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design

IEEE Transactions on Computers
b-adjacent error correction

IBM Journal of Research and Development

Algorithm-Based Fault Tolerance for Matrix Operations

IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

IEEE Transactions on Computers
On CMOS totally self-checking circuits

ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production

Quantified Score

Hi-index	14.99

Visualization

Abstract

Self-checking approaches developed so far deal with a gate level representation of logical circuits. They do not account for constraints which may result from an implementation by integrated circuits. This paper is concerned with such practical problems and their respective significance.