Optimum test patterns for parity networks

Authors:
D. C. Bossen;D. L. Ostapko;A. M. Patel
Affiliations:
IBM Laboratories, Poughkeepsie, New York;IBM Laboratories, Poughkeepsie, New York;IBM Laboratories, Poughkeepsie, New York
Venue:
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Year:
1970

Citing 0
Cited 6

Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes

IEEE Transactions on Computers
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks

IEEE Transactions on Computers
Design and Application of Self-Testing Comparators Implemented with MOS PLA's

IEEE Transactions on Computers
Robust tests for parity trees

ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Detecting bridging faults with stuck-at test sets

ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Self-Testing Embedded Parity Checkers

IEEE Transactions on Computers

Quantified Score

Hi-index	0.01

Visualization

Abstract

The logic related to the error detecting and/or correcting circuitry of digital computers often contains portions which calculate the parity of a collection of bits. A tree structure composed of Exclusive-OR gates is used to perform this calculation. Similar to any other circuitry, the operation of this parity tree is subject to malfunctions. A procedure for testing malfunctions in a parity tree is presented in this report.