A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
IEEE Transactions on Computers
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems
Journal of Signal Processing Systems
Residue Number Systems: Theory and Implementation
Residue Number Systems: Theory and Implementation
Variation-aware low-power synthesis methodology for fixed-point FIR filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved area-efficient weighted modulo 2n+ 1 adder design with simple correction schemes
IEEE Transactions on Circuits and Systems II: Express Briefs
Multiple constant multiplication through residue number system
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques of sharing of subexpressions in the multiplier block (MB), to its optimized usage in the MB and accumulation pipeline hardware design. As a result, we propose a common subexpression elimination (CSE) based synthesis technique for RNS-based MBs, along with a high-performance RNS-based FIR filter architecture that employs RNS arithmetic principles but implements them mainly using more efficient 2's complement hardware. Several filters with numbers of taps ranging from 25 to 326 and dynamic ranges from 24 to 50 bits have been synthesized using TSMC 90~nm LP kit and Cadence RTL Compiler. Comparison of power, delay, and area of the new filters implemented using the 4- and 5-moduli RNSs against various equivalent 2's complement counterparts show uniform improvement in performance and power efficiency, often accompanied by significant reduction in area/power consumption as compared to 2's complement implementations. We observed up to 22% improvement in peformance (19% reduction in area) within bounded power envelope, or up to 14% reduction in power consumption (12% reduction in area) at same frequency.