Journal of the ACM (JACM)
Speedup of ordinary programs
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Time and Parallel Processor Bounds for Fortran-Like Loops
IEEE Transactions on Computers
Hi-index | 14.98 |
A parallel method of execution for a certain class of loops containing IF statements is described. We replace a given loop by an equivalent set of five loops, four of which are vectorizable; the fifth loop is executed in hardware as a Boolean recurrence. The proposed architecture handles all loops that produce recurrences with order =m, a hardware parameter.