A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Software Implementation of the NIST Elliptic Curves Over Prime Fields
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm
IEEE Transactions on Computers
Parametric, Secure and Compact Implementation of RSA on FPGA
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
An optimized hardware architecture for the montgomery multiplication algorithm
PKC'08 Proceedings of the Practice and theory in public key cryptography, 11th international conference on Public key cryptography
New Hardware Architectures for Montgomery Modular Multiplication Algorithm
IEEE Transactions on Computers
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
New directions in cryptography
IEEE Transactions on Information Theory
Efficient FPGA implementation of montgomery multiplier using DSP blocks
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(p) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form β = 2k. The design uses only three k x k multipliers and three 2k-bit adders. The hardware organization of the multiplier maximizes the use of the multipliers processing iteratively the multiplicand, multiplier and modulus. The parametric design allows to study area-performance trade offs, in order to meet system requirements such as available resources, throughput, and efficiency. The proposed multiplier achieves a 1024-bit modular multiplication in 15.63 μs using k = 32. Compared to the most compact FPGA implementation previously reported, our proposed design uses 79% less FPGA resources with better efficiency expressed as Mbps/Slice.