Efficient FPGA implementation of montgomery multiplier using DSP blocks

Authors:
Arpan Mondal;Santosh Ghosh;Abhijit Das;Dipanwita Roy Chowdhury
Affiliations:
Department of Computer Science and Engineering, IIT Kharagpur, WB, India;Department of Computer Science and Engineering, IIT Kharagpur, WB, India;Department of Computer Science and Engineering, IIT Kharagpur, WB, India;Department of Computer Science and Engineering, IIT Kharagpur, WB, India
Venue:
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Year:
2012

Citing 1
Cited 1

New Hardware Architectures for Montgomery Modular Multiplication Algorithm

IEEE Transactions on Computers

A compact FPGA-based montgomery multiplier over prime fields

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

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Abstract

In this paper, an efficient Montgomery modular multiplier is designed exploiting the efficiency of inbuilt multiplier and adder soft-cores of DSP blocks. 256×256 bit multiplier has been implemented with (i) fully parallel, (ii) pipelined and (iii) semi parallel architectures that consumes upto 16 DSP48E1 64×64 bit soft-cores provided by Xilinx 12.4 ISE Design Suite. Performances with respect to area, operating frequency and design latency have been compared.