A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
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In the manufacture of chips and modules, it is important to minimize defects in order to maximize quality levels and product reliability at each level of product assembly (chips, module, card, system). These objectives are best achieved by controlling defects through manufacturing process controls and testing at the lowest possible level of assembly. Defective product remaining after test and inspection must be repaired or discarded. The ability to detect and reduce or eliminate these defects is crucial to ensuring maximum product quality. The amount of such defective product is typically described quantitatively in terms of statistical sampling plans. The problem with such approaches is that the absolute defect level is imprecisely defined. This paper defines an absolute number for such product defects, which we will call "product quality level" (PQL). PQL categories found in logic chips and modules after completion of electrical testing are described and a methodology for the monitoring and control of the PQL in chips is presented. The impact of chip defects on module, card, and system performances is discussed with the aid of examples. By using the described comprehensive design, process control, testing, and user-feedback approach at each assembly level, final product can be manufactured with the lowest possible level of defects that must then be repaired at the machine level.