Logic design of digital systems
Logic design of digital systems
Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
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This paper introduces techniques from combinatorial and algebraic topology to help in explaining and measuring the performance of modern logic minimizers. The concepts of simple cubical homotopy and the Euler—Poincare characteristic of a logic cover are defined and analyzed. In particular, simple cubical homotopy is related to the minimization algorithms Espresso—EXACT and Roth's Extraction Algorithm. Experimental results on the Euler—Poincare characteristic, along with a new measure, the Euler Ratio are related to the function complexity concepts of “Cyclic constraints” in Espresso_EXACT, the “CyclicKernel” in Roth's Extraction Algorithm, and “cubical homotopy” introduced in this paper.