Proceedings of the conference on Design, automation and test in Europe
IEEE Spectrum
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
Fault Tolerance in the WebCom Metacomputer
ICPPW '01 Proceedings of the 2001 International Conference on Parallel Processing Workshops
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
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We propose a new survival architecture that analyzes a network environment and decides the classification of the faults through the packet flow for network processors. The proposed architecture recognizes the unusual state in the network when the packet, which is the input of a network processor, can not be transmitted for a while. The network processor with the abnormality of the packet transmission detection generates a test packet so as to report the abnormality and to collect the information for the analysis of the source and the classification of the faults. According to this process, the proposed architecture derives the cause of the fault and the solution. Finally, the stability of the packet process is increased because the viability of the network processor is increased.