A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
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Recently, we introduced a comprehensive fault model of CMOS circuits wherein CMOS stuck-open (sop) faults in combinational circuits are transformed into the classical TTL Stuck-at (s-a) faults. Thereby makes testing of CMOS combinational circuits equivalent to testing the transformed TTL sequential circuits for s-a faults. This paper extends our previous work to cover testing of CMOS combinational networks for multiple faults. The basic strategy is to employ our comprehensive fault model and then to apply the path sensitization procedure for the dominant faults. In addition, it is also demonstrated as to how the model could be utilized in testing CMOS sequential circuits which are assumed to be designed using the LSSD technique. Several examples are included to illustrate the versatability and usefulness of our fault models and testing algorithms.