All points addressable raster display memory
IBM Journal of Research and Development
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Multipurpose DRAM architecture for optimal power, performance, and product flexibility
IBM Journal of Research and Development - Special issue: IBM CMOS technology
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
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A "System on a Chip" is described, which integrates 16Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video Digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application Specific Integrated Circuit (ASIC) techniques are employed, using multiple DRAM macros with Built-in Self Test (BIST), full Level-Sensitive Scan Design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.