A Rule-Based Design-for-Testability Rule Checker
IEEE Design & Test
Design For Test Calculus: An algorithm for DFT rules checking
DAC '83 Proceedings of the 20th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
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The test protocol for a serial scan design comprises the serial scan-in, parallel measure & capture, and serial scun-out operations. Through symbolic simulation of the protocol, compliance with scan design rules can be verified. For example, simulation of the scan-in operation should establish an arbitrary known state in all sequential cells within the design. A cell whose state is not controllable represents a design rule violation. This approach is both more flexible and more robust than previous work, and addresses current issues with the integration of internal scan and boundary scan. Further, the approach links the tasks of design rule checking und the formatting of the output of Automatic Test Pattern Generation (ATPG) into a scan test program. This approach has been opplied successfully to a wide variety of designs, up to 700K gates.