The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
An interpreter for general netlist design rule checking
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A Rule-Based Design-for-Testability Rule Checker
IEEE Design & Test
A simulation-based protocol-driven scan test design rule checker
ITC'94 Proceedings of the 1994 international conference on Test
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A new one-pass algorithm for checking networks for compliance to a set of Design for Test (DFT) rules is presented. The algorithm is based on a “Design For Test Calculus” which defines various types of signals and nodes in the network, signal sets attached to node's inputs and outputs, and rules for transferring signal sets through nodes. The rule checking is accomplished by examining the characteristic contents of the signal sets transferred. The calculus is capable of handling a wide variety of “test point flip-flops” and test access schemes, and has features that make hierarchical rule checking feasible.