A formal method for computer design verification

  • Authors:
  • Vijay Pitchumani;Edward P. Stabler

  • Affiliations:
  • -;-

  • Venue:
  • DAC '82 Proceedings of the 19th Design Automation Conference
  • Year:
  • 1982

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Abstract

A formal computer design verification method based on Floyd's inductive assertion technique9 is presented as an alternative or at least a supplement to simulation. The semantics of a register transfer language is defined formally. It specifies how machine variables and time change. Hardware descriptions in this language may contain assertions. The formal definition of the language can then be used for automatic verification of logical correctness and realtime performance of the design.