Verification of combinational logic in Nuprl
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
A new method for verifying sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A formal method for computer design verification
DAC '82 Proceedings of the 19th Design Automation Conference
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