Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
RISE++: A Symbolic Environment for Scan-Based Testing
IEEE Design & Test
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
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The author presents an architecture for implementing scan technology in a state-of-the-art workstation that uses a single resource to control scan and clock functions and perform pseudorandom testing of individual chips and boards. The testing approach, which is based on the use of a linear-feedback shift register, also features the ability to capture test results and compress them into a single signature for comparison with a known 'golden-circuit' signature. The author describes an application for testing the Apollo DN10000 and presents a list of design rules for pseudorandom testing at the board level. He discusses communication with scan and clock resources, timing relationships for scan operations, problems encountered, and design-for-testability issues in some depth.