A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
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With the ever-increasing density, development cost, and turn-around time of VLSI chips it becomes increasingly important to have a design verification methodology which enables first-pass chips to be fully functional. The strategy discussed in this paper exploits the best attributes of the two traditional methods of design verification (i.e., software simulation and hardware modeling). Software simulation was chosen for its capability in the area of delay analysis and early functional checking. An automatically generated nodal-equivalent hardware model was built to provide the vehicle on which exhaustive functional checking could be performed. The model also operated as early user hardware on which functions such as operating systems, I/O adapters, and a floating-point feature could be tested. A technique known as interface emulation was used on certain well-defined subsystems to facilitate a shorter verification schedule through parallel debug efforts.