Logic design automation of MOS combinational networks with fan-in, fan-out constraints
DAC '78 Proceedings of the 15th Design Automation Conference
Logic design automation of diagnosable MOS combinational logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
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Since the technology has gone into large and very large scale integration (LSI and VLSI), one important problem is the testing of such integrated circuits. Recently, increasing interest and attention has been given to “design for testability” or design of diagnosable digital networks.Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks have recently been presented by these authors. In this paper, we discuss the testing aspect of these designed networks.A basic cell model was presented for the purpose of simulation and test generation. Procedures for describing the generation of a complete fault detection set for the complex cell are given. Both minimal and near-minimal solutions are presented for both fan-out free and arbritrary complex cells respectively. Also, a procedure for generating the fault detection test list for arbitrary combinational networks is given also.Some future work problems are presented and the application of this design technique for improving the LSI and VLSI testability is introduced.