Testability analysis of MOS VLSI circuits

Authors:
David M. Singer
Affiliations:
AT&T Bell Laboratories, Murray Hill, New Jersey
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

Citing 2
Cited 0

SCOAP: Sandia controllability/observability analysis program

DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability

DAC '77 Proceedings of the 14th Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Modeling problems that are encountered in applying an existing testability measure to MOS circuits are identified. These problems arise primarily because MOS circuits can implement functions that cannot be modeled at the logic gate level. Models for the testability analysis of circuits with memories (RAM and ROM), buses, and transmission gates are developed. In addition, the use of the controllability/observability measures in analyzing the testability of stuck-at-faults, and in defining an overall circuit testability index is discussed.