A concept for test and reconfiguration of a fault-tolerant VLSI processor system

Authors:
K. E. Grosspietsch;J. Kaiser;E. Nett
Affiliations:
-;-;-
Venue:
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Year:
1980

Citing 6
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Abstract

The following paper is to present a test and reconfiguration strategy for fault-tolerant VLSI processor systems. This is accomplished with respect to the requirements imposed by the VLSI technology. The proposed concept is exemplified by a model composed of four microprogrammable processors each with a local memory. The test strategy of a gradually expanding hardcore is applied where the central hardcore consists of a small test unit of low complexity. This test unit enables each processor to diagnose autonomously its data path structure and its associated local memory. A particular reconfiguration scheme is proposed for these components. It is implemented at microprogram level. As a result, compared with other fault-tolerance techniques, system reliability is considerably improved.