Digital Circuits and Logic Design
Digital Circuits and Logic Design
Design of Diagnosable Sequential Machines Utilizing Extra Outputs
IEEE Transactions on Computers
Algorithms ror Designing Fault-Detection Experiments ror Sequential Machines
IEEE Transactions on Computers
Fault Detection of Binary Sequential Machines Using R-Valued Test Machines
IEEE Transactions on Computers
A Method for the Design of Fault Detection Experiments
IEEE Transactions on Computers
Distinguishing Sets for Optimal State Identification in Checking Experiments
IEEE Transactions on Computers
IEEE Transactions on Computers
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
Checking Experiments ror Sequential Machines
IEEE Transactions on Computers
Sequential Machines Capable of Fault Diagnosis
IEEE Transactions on Computers
Fault-Detection Experiments for Parallel-Decomposable Sequential Machines
IEEE Transactions on Computers
Fault detecting experiments for sequential circuits
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
An Improved Bound on the Length of Checking Experiments for Sequential Machines with Counter Cycles
IEEE Transactions on Computers
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
Pseudo-exhaustive testing of sequential machines using signature analysis
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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By augmenting a given sequential machine M with two extra input symbols Ie1 and Ie2 and with one extra output terminal Z', a method is developed in this paper for designing an efficient checking experiment for the machine M and for its fault diagnosis to cover the types of faults which may result in an increase in the number of states of the original machine M. The method is an extension of the works of Fujiwara et al.[6], and the scheme of modification never alters the modified machine M' from its easily testable nature as defined by Fujiwara et al [16]. The checking sequences exhibit remarkable savings of the number of input symbols for many sequential machines having a large number of states as compared to that of Fujiwara et al [16].