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This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability andSecurity Engine (RSE), which is implemented as an integralpart of a modern microprocessor. The RSE interacts with theprocessor through an input/output interface. The CHECKinstruction, a special extension of the instruction set architectureof the processor, is the interface of the application withthe RSE. The detection mechanisms described here in detailare: (1) the Memory Layout Randomization (MLR) module,which randomizes the memory layout of a process in order tofoil attackers who assume a fixed system layout, (2) the DataDependency Tracking (DDT) module, which tracks the dependenciesamong threads of a process and maintains checkpointsof shared memory pages in order to rollback thethreads when an offending (potentially malicious) thread isterminated, and (3) the Instruction Checker module (ICM),which checks an instruction for its validity or the control-flowof the program just as the instruction enters the pipeline forexecution. Performance simulations for the studied modulesindicate low overhead of the proposed solutions.