Warm-Up Simulation Methodology for HW/SW Co-Designed Processors

  • Authors:

  • Aleksandar Branković;Kyriakos Stavrou;Enric Gibert;Antonio González

  • Affiliations:

  • Universitat Politècnica de Catalunya, Spain;Intel Barcelona Research Center, Intel Labs Barcelona, Spain;Intel Barcelona Research Center, Intel Labs Barcelona, Spain;Universitat Politècnica de Catalunya, Spain and Intel Barcelona Research Center, Intel Labs Barcelona, Spain

  • Venue:
  • Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization
  • Year:
  • 2014

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Abstract

Evaluation techniques in microprocessor design are mostly based on simulating selected application samples using a cycle-accurate simulator. In order to achieve accurate results, microarchitectural structures are warmed-up for a few million instructions prior to statistics collection. Unfortunately, this strategy cannot be applied to HW/SW co-designed processors, in which a Transparent Optimization software Layer (TOL) translates and optimizes code on-the-fly from a guest ISA to an internal host custom microarchitecture. We show that the warm-up period in this case needs to be 3-4 orders of magnitude longer than what is needed for traditional microprocessor designs because the TOL state needs to be warmed-up as well. In this paper, we propose a novel simulation technique for HW/SW co-designed processors based on adapting the optimization promotion thresholds using high level application statistics in order to find the best trade-off between accuracy and simulation cost. In particular, the proposed technique reduces the simulation cost by 65X with an average error of just 0.75%. Furthermore, as opposed to other alternatives, the proposed technique satisfies the additional requirement of allowing evaluation using different TOL and microarchitectural configurations.