Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State

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ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Year:
2001

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Abstract

Abstract: A new asynchronous pipeline design is introduced for high-speed applications. The pipeline uses simple transparent latches in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. This simple stage structure ...