Characterizing and Comparing Prevailing Simulation Techniques

  • Authors:

  • Joshua J. Yi;Sreekumar V. Kodakara;Resit Sendag;David J. Lilja;Douglas M. Hawkins

  • Affiliations:

  • Freescale Semiconductor, Inc., Austin, TX;University of Minnesota, Minneapolis, MN;University of Rhode Island, Kingston, RI;University of Minnesota, Minneapolis, MN;University of Minnesota, Minneapolis, MN

  • Venue:
  • HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
  • Year:
  • 2005

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Abstract

Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not been evaluated is their accuracy relative to the reference input set, and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize the reduced input set, truncated execution, and sampling simulation techniques while also examining their speed versus accuracy trade-off and configuration dependence. Finally, to illustrate the effect that a technique could have on the apparent speedup results, we quantify the speedups obtained with two processor enhancements. The results show that: 1) The accuracy of the truncated execution techniques was poor for all three characterization methods and for both enhancements, 2) The characteristics of the reduced input sets are not reference-like, and 3) SimPoint and SMARTS, the two sampling techniques, are extremely accurate and have the best speed versus accuracy trade-offs. Finally, this paper presents a decision tree which can help architects choose the most appropriate technique for their simulations.