Phase guided sampling for efficient parallel application simulation

  • Authors:
  • Jeffrey Namkung;Dohyung Kim;Rajesh Gupta;Igor Kozintsev;Jean-Yves Bouget;Carole Dulong

  • Affiliations:
  • University of California San Diego;University of California San Diego;University of California San Diego;Intel;Intel;Intel

  • Venue:
  • CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
  • Year:
  • 2006

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Abstract

Simulating chip-multiprocessor systems (CMP) can take a long time. For single-threaded workloads, earlier work has shown the utility of phase analysis, that is identification of repetitive program behaviors, in reducing overall simulation time while maintaining an acceptable loss in accuracy. To cope with multithreaded workloads, a combination of phases from all executing threads must be taken into consideration since inter-thread interference may distort the homogeneity of each phases' true performance. Unfortunately, phase analysis does not work for multithreaded (MT) workloads because the possible phase combinations in an inherently nondeterministic execution model grows exponentially with the number of threads. To this end, we propose a new technique to reduce the number of simulation samples by synthesizing samples from similar phase combinations. We present a simple cost function for measuring the similarity between phase combinations and by using the individual thread samples from the similar phase combinations, a new sample can be constructed. This cost function provides a convenient control knob for exploiting tradeoffs between simulation speed and accuracy. Our experimental results show that in most cases, properly setting the cost function's threshold can yield a reduction in sampling by 90%, while maintaining error to less than 5%.