Statistical Simulation of Multithreaded Architectures

  • Authors:

  • Joshua L. Kihm;Daniel A. Connors

  • Affiliations:

  • University of Colorado at Boulder Department of Electrical and Computer Engineering UCB 425, Boulder, CO.;University of Colorado at Boulder Department of Electrical and Computer Engineering UCB 425, Boulder, CO.

  • Venue:
  • MASCOTS '05 Proceedings of the 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
  • Year:
  • 2005

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Abstract

Detailed, cycle-accurate processor simulation is an integral component of the design and study of computer architectures. However, as the detail of simulation and processor design size increase, simulation times grow exponentially, and it becomes increasingly necessary to find fast, efficient simulation techniques that still ensure accurate results. At the same time, multithreaded multi-core designs are increasingly common, and require increased experimental design evaluation for a number of reasons including higher system complexity, interaction of multiple co-scheduled application threads, and workload selection. Although several effective simulation techniques exist for single-threaded architectures, techniques have not been effectively applied to the simulation of multithreaded and multi-core architecture models. Moreover, multithreaded processor simulation introduces unique challenges in all simulation stages. This work introduces systematic extensions of commonly-used statistical simulation techniques to multithreaded systems. The contributions of this work include: tailoring simulation fast-forwarding for individual threads, the effects of cache warming on application threads, and an analysis of the primary issues of efficient multithreaded simulation.