Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Communications of the ACM
Region-based compilation: an introduction and motivation
Proceedings of the 28th annual international symposium on Microarchitecture
Register promotion in C programs
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Optimizing direct threaded code by selective inlining
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Machine-adaptable dynamic binary translation
DYNAMO '00 Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization
Dynamic Binary Translation and Optimization
IEEE Transactions on Computers
Introduction to the Theory of Computation
Introduction to the Theory of Computation
FX!32: A Profile-Directed Binary Translator
IEEE Micro
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Retargetable and reconfigurable software dynamic translation
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Register Liveness Analysis for Optimizing Dynamic Binary Translation
WCRE '02 Proceedings of the Ninth Working Conference on Reverse Engineering (WCRE'02)
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Hardware Support for Control Transfers in Code Caches
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems
Proceedings of the International Symposium on Code Generation and Optimization
Engineering A Compiler
Generating low-overhead dynamic binary translators
Proceedings of the 3rd Annual Haifa Experimental Systems Conference
Binary translation using peephole superoptimizers
OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
Performance characterization of the 64-bit x86 architecture from compiler optimizations' perspective
CC'06 Proceedings of the 15th international conference on Compiler Construction
StarDBT: an efficient multi-platform dynamic binary translation system
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
| Hi-index | 0.00 |
Dynamic binary translation (DBT) has been widely used as a means to run applications created for one instruction-set architecture (ISA) on top of processors with a different ISA. Given the great amount of legacy software developed for PCs, based on the Intel® Architecture (IA) ISA, a lot of attention has been given to translating IA to other ISAs. The recent trends in industry for both smaller ultra-mobile PCs and more powerful embedded and mobile internet devices (e.g. smartphones) are blurring the frontiers between these distinct markets. As a result, this market convergence is creating great interest in DBT from ISAs that currently dominate the embedded and mobile-internet-device markets (e.g. ARM, MIPS, and PowerPC) to IA. This paper investigates the main challenges that arise when targeting IA in a DBT. We identify the two key issues in efficiently translating from other ISAs to IA: IA's small number of registers, and its condition-code handling mechanism. To address these issues, we propose a combination of software and hardware solutions. Although motivated by IA, these techniques are not IA-specific, and they can be applied to other architectures with similar limitations to make them better DBT-targets. We have prototyped these techniques in Harmonia, an ARM-to-IA DBT tool based on open-source QEMU. Our experiments show that Harmonia achieves an average of 55% (up to 164%) of the performance of highly optimized native binaries, and an average speedup of 2.2 x on top of the baseline QEMU.