Proceedings of the 8th ACM International Conference on Computing Frontiers
Issues and support for dynamic register allocation
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Dynamic binary translators compile machine code froma source architecture to a target architecture at run time.Due to the hard time constraints of just-in-time compilationonly highly efficient optimization algorithms can beemployed. Common problems are an insufficient numberof registers on the target architecture and the different handlingof condition codes in source and target architecture.Without optimizations useless stores and computations aregenerated by the dynamic binary translator and cause significantperformance losses. In order to eliminate these use-lessoperations, a very fast liveness analysis is required.We present a dynamic liveness analysis algorithm thattrades precision for fast execution and conducted experimentswith the SpecInt95 benchmark suite using our PowerPCto Alpha translator. The optimizations reduced thenumber of stores by about 50 percent. This resulted in aspeed-up of 10 to 30 percent depending on the target machine.The dynamic liveness analysis results are very closeto the most precise solution.