Tuning data replication for improving behavior of MPSoC applications

Authors:
O. Ozturk;M. Kandemir;M. J. Irwin;I. Kolcu
Affiliations:
The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA;The Pennsylvania State University, University Park, PA;UMIST, Manchester, UK
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

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Abstract

Maintaining cache coherence can be very costly for on-chip multiprocessors from an energy perspective. Observing this, we propose a compiler-directed strategy that replicates array data in cache memories of its potential consumer processors at the time the data is brought from off-chip memory. The goal is to eliminate the energy costs associated with bus snooping without negatively impacting overall performance. Our strategy can perform a much better job as compared to static replication strategies, where each array element is replicated based on the same fixed policy.