A Chip-Multiprocessor Architecture with Speculative Multithreading
IEEE Transactions on Computers
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Early Register Deallocation Mechanisms Using Checkpointed Register Files
IEEE Transactions on Computers
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Transactional Memory, 2nd Edition
Transactional Memory, 2nd Edition
Circuit design of a dual-versioning L1 data cache
Integration, the VLSI Journal
Circuit design of a novel adaptable and reliable L1 data cache
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32-KB dual-versioning L1 data cache with 45-nm CMOS technology at 2GHz processor frequency and 1V supply voltage, which we describe in detail. We also introduce three well-known use cases that make use of optimistic concurrency execution and that can benefit from our proposed design. Moreover, we evaluate one of the use cases to show the impact of the dual-versioning cell in both performance and energy consumption. Our experiments show that large speedups can be achieved with acceptable overall energy dissipation.