Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Software pipelining loops with conditional branches
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Software pipelining: a comparison and improvement
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A VLIW architecture based on shifting register files
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Hierarchical Clustered Register File Organization for VLIW Processors
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Multi-Shared Register File Structure for VLIW Processors
Journal of Signal Processing Systems
A compile-time managed multi-level register file hierarchy
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
ACM Transactions on Computer Systems (TOCS)
SCRF: a hybrid register file architecture
PaCT'07 Proceedings of the 9th international conference on Parallel Computing Technologies
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This paper presents a novel architecture of register files that combines the local register files and the global register file for clustered VLIW (Very Long Instruction Word) processors. The communication between function units through global register file will be more efficient. The concept of associate register is introduced for this architecture. This makes it possible to write a result to two destination registers in one operation, which can efficiently speed up the software pipelining.