Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
WCDMA for UMTS: Radio Access for Third Generation Mobile Communications
WCDMA for UMTS: Radio Access for Third Generation Mobile Communications
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
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In this paper, dual antenna receiver architectures are studied including RAKE, chip-level linear equalizer, and their combination. The arithmetic complexity of single and dual antenna receiver methods is analyzed. Cost of such receivers when implemented with customized hardware or software on application-specific instruction set processors (ASIP) is estimated. The study shows that feasible dual antenna detection can be obtained with less than 70% additional costs. More flexible implementation supporting several standards can be obtained with software but it requires higher power consumption due to additional memory.