Fuzzy sets, uncertainty, and information
Fuzzy sets, uncertainty, and information
PPOPP '95 Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming
Journal of Parallel and Distributed Computing
Fuzzy set theory: foundations and applications
Fuzzy set theory: foundations and applications
Simulation/evaluation environment for a VLIW processor architecture
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
Advanced compiler design and implementation
Advanced compiler design and implementation
Optimal integrated code generation for clustered VLIW architectures
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Introduction to Algorithms
Compiler Scheduling for STA-Processors
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Embedded Microcomputer Systems: Real Time Interfacing
Embedded Microcomputer Systems: Real Time Interfacing
Code generation for STA architecture
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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High quality code generation for DSPs that consist of irregular architectures is a challenge in terms of problem complexity. Since such problems are divided into several separated subtasks in the traditional compiler backends, the code quality is decreased owing to the ignorance of the interdependencies among these subtasks. Thus, an integrated compiler backend by using fuzzy control system is developed for an irregular architecture which is called Synchronous Transfer Architecture (STA). According to the experimental results, our novel method is proved to be more efficient than the traditional method. The code size and execution time of the generated code are reduced to be about 42.7% to 62.5% of those achieved by traditional compiler backend. Moreover, the power consumption is greatly reduced concerning the efficient utilization of the STA data paths.